1. Field of the Invention
The present invention relates to a logic controller and, more particularly, to a low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock.
2. Description of the Related Art
A logic controller is a device that generates a number of output signals which, in turn, are used to control a number of external logic devices. A logic controller that implements “thermometer type” control logic can be used to generate output signals that monotonically increase or decrease, just like the temperature on a mercury thermometer. As a result of this behavior, this type of logic controller is often referred to as a “thermometer controller.”
The output signals of a thermometer controller represent the bits of a thermometer code. The output signals/bits include a first number of output signals/bits that have a first logic state, such as a logic high, followed by a second number of output signals/bits that have a second logic state, such as a logic low (e.g., four thermometer bits, Y0–Y3, could have the logic state 1100).
Thus, taken together, the output signals/bits behave like the temperature indication on a mercury thermometer, where increasing the value of the code is representative of the temperature rising, and decreasing the value of the code is representative of the temperature falling. In addition, the highest output signal/bit that is active, including all of the lower output signals/bits (which must also be active), is representative of the current temperature.
During normal operation, when a thermometer code increases, only one output signal/bit changes state from low to high. The output signal/bit that changes state is the logic zero in the code that lies adjacent to a logic one (e.g., from state 1100 to state 1110).
Similarly, when a thermometer code decreases, only one output signal/bit changes state from high to low. The output signal/bit that changes state is the logic one in the code that lies adjacent to a logic zero, (e.g., from state 1100 to state 1000).
One of the benefits of a thermometer controller is that its output signals/bits are gray coded. As a result, the output signals/bits cannot produce any glitches when they are decoded by external logic gates. This feature is especially important in control applications that attempt to establish and maintain an optimal “set point” within a range of output values. These control applications often attempt to generate a new output value by interpolating between two or more values within the output range.
FIG. 1 shows a block diagram that illustrates a prior-art, thermometer controller 100. Referring to FIG. 1, controller 100 receives four control signals and generates eight output signals/bits Y0–Y7 in response. The four control signals include a clock signal CLK, an up signal UP, a down signal DWN and a clear signal CLR. The clear signal CLR resets each of the output signals/bits Y0–Y7 to the logic low state, which is the inactive state for these signals.
To increase the value of the thermometer code, the up signal UP must be active during a given clock cycle. For example, assuming that the output signals Y0–Y3 are initially active in a given clock cycle, and the up signal UP is also active, the output signals Y0–Y3 will remain active in the next clock cycle, and the next highest output signal Y4 will also become active in the next clock cycle (e.g., state 11110000 goes to state 11111000).
To decrease the value of the thermometer code, the down signal DWN must be active during a given clock cycle. For example, assuming that the output signals Y0–Y6 are initially active in a given clock cycle, and the down signal DWN is also active, the output signals Y0–Y5 will remain active in the next clock cycle, but the highest active output signal Y6 will become inactive in the next clock cycle (e.g., state 11111110 goes to state 11111100).
Alternatively, if the up and down signals UP and DWN are both inactive during a given clock cycle, the thermometer code will remain the same in the next clock cycle. For example, if the output signals Y0–Y4 are active in a given clock cycle, and the up and down signals UP and DWN are both inactive in that clock cycle, then the output signals Y0–Y7 will remain unchanged in the next clock cycle (e.g., state 11111000 goes to state 11111000).
One drawback of controller 100 is that it can only generate nine different temperature codes (including the case where all of the output signals are inactive). One approach to overcoming this limitation is to employ a code segmentation approach.
FIG. 2 shows the block diagram of a prior-art thermometer controller 200. Controller 200 is the same as controller 100, except that controller 200 also generates S0 and S1, two additional temperature output signals/bits. S0 and S1 represent four encoded temperature ranges that are usually referred to as temperature “segments”.
Temperature segment signals/bits S0 and S1 extend the temperature range of controller 200 by adding only a minimum number of additional outputs. For example, controller 200 has four temperature segments represented by the Gray-coded temperature segment signals/bits S0 and S1. The additional S0 and S1 bits allow controller 200 to output the equivalent of 36 different temperature values, as follows:
TemperatureSegmentS1S0Y0–Y700000000000 . . . 11111111 (9 temperatures)10100000000 . . . 11111111 (9 temperatures)21100000000 . . . 11111111 (9 temperatures)31000000000 . . . 11111111 (9 temperatures)
When there are only four encoded temperature segments, the segment outputs are usually referred to as temperature “quadrant” outputs, corresponding to the four quadrants of a circle (0°–90°, 90°–180°, 180°–270° and 270°–360°). Since the temperature segment/quadrant signals are Gray coded, the temperature segment/quadrant signals can be decoded by external logic gates without producing any output “glitches.” This is very important in many control applications, especially those related to switching DAC outputs.
FIG. 3 shows the block diagram of a prior-art thermometer controller 300. Referring to FIG. 3, controller 300 has a series of output circuits CT0–CTn that generate a series of output signals Y0–Yn. Output signals Y0–Yn represent a series of bits in a thermometer code (only five output signals/bits Y0–Y4 are shown for the sake of clarity).
As further shown in FIG. 3, the output circuits CT0–CTn include a series of flip-flops U0–Un (only five flip-flops U0–U4 are shown for the sake of clarity), and a corresponding series of multiplexers M0–Mn (only five multiplexers M0–M4 are shown for the sake of clarity). Each flip-flop U0–Un, in turn, has a Q output, a data input D, a clock input connected to receive a clock signal CLK, and a clear input connected to receive a clear signal CLR.
Each multiplexer M0–Mn has three data inputs, an up input connected to receive an up signal UP, a down input connected to receive a down signal DWN, and an output connected to the D input of the flip-flop in the same output circuit. Furthermore, the three data inputs of each multiplexer M0–Mn include a first input that is connected to the Q output of flip-flop in the same output circuit, a second input that is connected to the Q output of the flip-flop in the preceding output circuit, and a third input connected to Q output of the flip-flop in the next output circuit.
For example, the first input of multiplexer M2 of output circuit CT2 is connected to the Q output of flip-flop U2. The second input of multiplexer M2 of output circuit CT2 is connected to the Q output of flip-flop U1. The third input of multiplexer U2 of output circuit CT2 is connected to the Q output of flip-flop U3. During any given clock cycle, only one of the 3 multiplexer input signals is passed to the output of the multiplexer, according to the state of the UP/DWN signals.
For example, the three input sources to multiplexer M2 are selected as follows:
SelectedUPDWNInput SourceComment00Q output of U2 (Y2)Temperature does not change01Q output of U3 (Y3)Temperature decreases by one count10Q output of U1 (Y1)Temperature increases by one count11NoneIllegal input selection (not allowed)
Referring to the above table and to FIG. 3, it can be seen that the flip-flops U0–U4 of output circuits CT0–CT4 form a 5-bit bi-directional shift register that can implement one of the following three operations in any given clock period, depending upon the state of the up and down signals UP and DWN:
1)UP = 0, DWN = 0:Hold the present state,2)UP = 1, DWN = 0:Shift right by one bit, and3)UP = 0, DWN = 1:Shift left by one bit.
During normal operation, when the clear signal CLR is activated, the output signals Y0–Yn (Y0–Y4 in FIG. 3) are inactivated to their cleared state. This sets the thermometer code to zero.
The value of the thermometer code is increased by performing a right shift operation in response to the up signal UP. Thus, when the up signal UP is active, the multiplexers M1–Mn in the output circuits CT1–Crn pass the logic states of the Q outputs of the flip-flops U0–Un−1 in the preceding output circuits CT0–CTn−1, while the multiplexer M0 in output circuit CT0 passes a logic high represented by the power supply voltage VDD.
For example, consider the case where the output signals/bits Y0–Y3 are active and the output signal/bit Y4 is inactive. When the up signal UP is active, the multiplexer M0 of output circuit CT0 passes the active state generated by the power supply voltage VDD, the multiplexer M1 of output circuit CT1 passes the active state generated by the Q output of flip-flop U0 of output circuit CT0, and the multiplexer M2 of output circuit CT2 passes the active state generated by the Q output of flip-flop U1 of output circuit CT1.
Furthermore, the multiplexer M3 of output circuit CT3 passes the active state generated by the Q output of flip-flop U2 of output circuit CT2, and the multiplexer M4 of output circuit CT4 passes the active state generated by the Q output of flip-flop U3 of output circuit CT3. As a result, on the next clock edge, the output signal Y4 of output circuit CT4 becomes active, thereby increasing the value of the thermometer code from state 11110 to state 11111.
The value of the thermometer code is decreased by performing a left shift operation in response to the down signal DWN. When the down signal DWN is active, the multiplexers M0÷Mn−1 in the output circuits CT0–CTn−1 pass the logic states of the Q outputs of the flip-flops U1–Un of the next output circuits CT1–CTn, while the multiplexer M4 in output circuit CT4 passes a logic low represented by ground VSS.
For example, consider the case where the output signals/bits Y0–Y3 are active and the output signal/bit Y4 is inactive. When the down signal DWN is active, the multiplexer M0 of output circuit CT0 passes the active state generated by the Q output of flip-flop U1 of output circuit CT1, the multiplexer M1 of output circuit CT1 passes the active state generated by Q output of flip-flop U2 of output circuit CT2, and the multiplexer M2 of output circuit CT2 passes the active state generated by Q output of flip-flop U3 of output circuit CT3.
Furthermore, the multiplexer M3 of output circuit CT3 passes the inactive state generated by Q output of flip-flop U4 of output circuit CT4, and the multiplexer M4 of output circuit CT4 passes the inactive state represented by ground VSS. As a result, on the next clock edge, the output signal Y3 of output circuit CT3 becomes inactive, thereby decreasing the value of the thermometer code from 11110 to 11100.
Furthermore, if the up and down signals UP and DWN are both inactive during a given clock cycle, the thermometer code will remain the same in the next clock cycle. Thus, when the up and down signals UP and DWN are both inactive, the multiplexers M0–Mn in the output circuits CT0–CTn pass the logic states of the Q outputs of the flip-flops U0–Un, respectively.
For example, consider the case where output signals Y0–Y3 are active and the output signal Y4 is inactive. When the up and down signals UP and DWN are both inactive, the multiplexers M0–M4 of output circuits CT0–CT4 pass the states generated by the output circuits CT0–CT4, respectively.
Logic controller 300 suffers from several disadvantages, including high power dissipation, high complexity and large chip area. The high power dissipation occurs because the clock signal CLK must constantly run and can not be stopped. Thus, because the clock signal CLK must drive all of the flip-flops U0–Un shown in FIG. 3, the clock signal CLK must constantly drive a large capacitance C.
This, in turn, results in high dynamic power dissipation, known as CV2F power, where C is the load capacitance being driven, V is the power supply voltage VDD, and F is the clock frequency. High dynamic power dissipation is especially disadvantageous in high-speed applications, where the clock frequency can be in the giga-hertz region.
Another disadvantage of logic controller 300 is the use of a three-input multiplexer that requires a large number of gates, adding additional complexity, additional power dissipation and additional chip area. FIGS. 4A–4B illustrate a prior-art, 3-input multiplexer 400. FIG. 4A shows a symbolic view, while FIG. 4B shows a schematic view.
As shown in FIGS. 4A–4B, multiplexer 400 generates an output signal OUT, while receiving an up signal UP, a down signal DWN, and three inputs A1, A2, A3. Furthermore, multiplexer 400 is implemented with a complex gate 410, which includes three AND gates and a NOR gate, plus three inverters 412, 414, and 416.
As a result of the disadvantages described above, there is a need for a more efficient thermometer controller.